TG170 PCB Board 10 Layers
Through hole design in high speed PCB
Via exist parasitic capacitance and parasitic inductance, in the design of high-speed digital circuit, the damage of via parasitic inductance is often greater than the influence of the parasitic capacitance. The parasitic series inductance it weakens the contribution of bypass capacitors, weakened filtering effect of the whole power supply system. We can use the following formula to calculate a simply via approximation of parasitic inductance: L = 5.08h(ln(4h/d)1) where L refers to the inductance of through hole, h is length of the hole, and d is the diameter of the central borehole. As can be seen from the formula, the diameter of through-hole has little influence on the inductance, while the length of through-hole has the greatest influence on the inductance.Still using the above example, hole on the inductance can be calculated as follows: L=5.08x0.050[ln(4x0.050/0.010) 1]=1.015nH.If the rise time of a signal is 1 ns, then the equivalent impedance of size:XL=πL/T10-90=3.19Ω. Such impedance in a high frequency current through could not be ignored, it is important to note that the bypass capacitor needs through two vias when connect power supply layer and formation, so the parasitic inductance of via will be multiplied.
Based on the above analysis of parasitic characteristics for through-hole, it can be seen that seemingly simple through-hole in high-speed PCB design often brings great negative effects on circuit design. In order to reduce the adverse effects of parasitic effect of through-hole, it can be done as far as possible in the design:
1, from two aspects of cost and signal quality into consideration, choosing reasonable size of the hole size. Such as the memory module of 6-10 layer PCB design, selecting 10/20 mil (drilling/pad) via is better, for some small size of PCB board with high density can also try using 8/18 mil hole. The current technology conditions, it is difficult to use smaller size for hole. The power supply or ground via can consider to use bigger size to reduce the impedance.
2. According to the two formulas discussed above, it can be concluded that use thinner PCB board is conducive to reduce parasitic parameters of through-hole.
3. Don't to change the layer of signal lines on PCB board, that is, donn't use unnecessary holes.
4. The pins between the power supply and the ground should be drilled as close as possible, and the shorter the lines between the power supply and the ground pin, the better, because they will lead to the increase of inductance. At the same time, the lines between power supply and ground should be as thick as possible to reduce impedance.
5, place some ground hole near the signal change layer to provide the latest circuit for signal. Even can place on PCB board of some redundant grounding via. The design discussed earlier via model is each layer having pads, sometimes, we can be certain of reducing the pads or delete them. Especially in the case of a hole density is very big, which can lead to to form a partition circuit fault trough in copper layer, to solve this problem we can move the hole position, also can consider to decrease the pad size of the hole in the copper layer.